FPGA

以下ソース

filter_top.v

`timescale 1ns / 1ps

module filter_top(
	input wire clk,
	output wire led
    );
//1秒ごとに1bitのイネーブル信号を送る。
reg [26:0] counter;
reg c_enable;
wire cc_enable;
assign cc_enable = c_enable;
//D-FF回路接続	 
DFF df0(.clk(clk),.D(cc_enable),.Q(led));


always@(posedge clk) begin
	if(counter==27'd99999999)begin
		counter <= 27'd0;
		c_enable <= ~c_enable;
	end
	else begin
		counter <= counter + 27'd1;
	end
end
	 


endmodule
      
      
	      

DFF.v

`timescale 1ns / 1ps
module DFF(
	input wire clk,
	input wire D,
	output reg Q
);
	always@(posedge clk)begin
		Q <= D;
	end

endmodule
      
      

filter_top.ucf

NET "clk" LOC = L15;
NET "led" LOC = U18;